1. Field of the Invention
Generally, the subject matter disclosed herein relates to the field of manufacturing integrated circuits, and, more particularly, to chemical mechanical polishing (CMP) or generally planarizing processes and tools used for the formation of advanced semiconductor features, such as gate electrode structures, in which different materials have to be concurrently removed.
2. Description of the Related Art
The fabrication of modern integrated circuits requires a plurality of individual process steps involving the deposition of conductive, semiconductive or insulating layers on an appropriate substrate. After the deposition of one or more materials, device features are produced by patterning or otherwise treating the materials with well-known means, such as photolithography and etching. As a consequence, by patterning a material layer or layer system, typically, a certain topography will be created that also affects deposition and patterning of subsequent layers. Since sophisticated integrated circuits require the formation of a plurality of subsequent levels, it has become standard practice to periodically planarize the surface of the substrate so as to provide well-defined conditions for the deposition and patterning of subsequent material layers.
In this respect, CMP has become a widely used process technique for reducing imperfections in the substrate topography caused by preceding processes in order to establish enhanced conditions for a subsequent process, such as photolithography and the like. The polishing process itself causes mechanical damage to the polished surface, however, in an extremely low range, i.e., at an atomic level, depending on the process conditions. Chemical mechanical polishing typically requires a substrate to be attached to a carrier, a so-called polishing head, such that the substrate surface to be planarized is exposed and may be placed against a polishing pad. The polishing head and polishing pad are moved relative to each other by usually individually controlling the movements of the polishing head and the polishing pad. Typically, the head and pad are rotated against each other while the relative motion is controlled to locally achieve a target material removal rate. During the polishing operation, a slurry solution that may include a chemically reactive agent and abrasive particles is supplied to the surface of the polishing pad, thereby initiating a chemical reaction with the exposed surface material and also creating a physical removal component by the abrasive particles, which may preferably act on the reaction product generated by the chemical reaction.
One problem involved in the chemical mechanical polishing of substrates is the very different removal rates of differing materials, such as of a metal and a dielectric material, or dielectric materials of different type, or dielectric materials and semiconductive materials.
The different removal rates may, thus, contribute to a pronounced surface topography, wherein, typically, the material having the higher removal rate is increasingly recessed, which may, thus, result in inferior process conditions for subsequent processes and performance of structural features. For example, when removing excess metal from a dielectric material layer having incorporated therein metal regions, at a final stage of the removal process, the dielectric material is increasingly exposed so that, in this phase of the polishing process, typically metal and dielectric material are present, wherein a certain overpolish time may then result in a certain degree of “dishing” of the metal region due to the higher removal rate compared to the dielectric material. On the other hand, since a certain degree of overpolished time is typically required for completely removing the metal material across the entire substrate surface, a certain amount of the dielectric material may also be removed, however, in a pattern related manner, thereby also contributing to a non-planar surface topography after the end of the polishing process. A pattern dependent removal rate may typically be observed for areas having a different ratio of materials that have to be concurrently polished at a certain process stage. That is, in areas with a high density of, for instance, metal regions, the fraction of metal material to dielectric material is different compared to an area in which a reduced number of metal features per unit area is present.
Consequently, although the CMP process technique is per se a promising approach for globally providing a planar surface topography, the removal of a material may require a specifically designed slurry solution, thereby enabling an appropriate adaptation of the process conditions to the specific manufacturing phase of a semiconductor device for one specific material, while the slurry may be less appropriate for the removal of another material. For example, by using a specifically designed slurry solution in combination with appropriately selected process parameters, such as down force, relative speed and the like, highly selective polishing recipes may be established, which may be advantageous for removing a material having a pronounced surface topography relative to an underlying material, which may act as a stop layer. For example, well-established and frequently used materials in semiconductor production are silicon dioxide and silicon nitride. Since these materials typically exhibit different removal rates for presently well-established CMP recipes, a well controllable selective removal process may be performed on the basis of CMP. For example, when forming sophisticated shallow trench isolation regions, a silicon nitride layer may typically act as a hard mask material during the etching of isolation trenches in the silicon layer and may also act as an efficient CMP stop layer after refilling the isolation trenches with a silicon dioxide material upon removing any excess portion thereof
In other situations, however, the different removal characteristics of silicon nitride and silicon dioxide may cause significant variations in device characteristics and may also negatively influence the further processing of complex semiconductor devices, in particular when even a third material has to be treated during a certain phase of the CMP process.
One important example for process conditions in which silicon nitride and silicon dioxide, in combination with a further material, may have to be removed in a highly non-selective manner is the exposure of a polysilicon material in a so-called replacement gate approach, which may frequently be used in sophisticated semiconductor devices, as will be explained in more detail with reference to FIGS. 1a-1c. 
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device 100 in an advanced manufacturing stage. As illustrated, the device 100 may comprise a substrate 101 and a semiconductor layer 102, such as a silicon layer, in and above which are formed circuit elements 130, which may represent any circuit elements, such as transistors, capacitors, resistors, electronic fuses and the like. In the example shown, the circuit features 130 are illustrated in the form of gate electrode structures of field effect transistors. The gate electrode structures 130 typically comprise a gate dielectric material 131, such as a silicon dioxide based material, possibly in combination with a high-k dielectric material, and a polysilicon material 132. Furthermore, typically, a dielectric cap material 133 in the form of silicon nitride is provided above the material 132. Furthermore, a sidewall spacer structure 134, for instance comprised of silicon nitride, silicon dioxide and the like, is formed on sidewalls of the gate electrode structures 130.
The gate electrode structures 130 may represent sophisticated circuit features with a critical dimension, i.e., a length, in FIG. 1a, the horizontal extension of the electrode material 132, of 40 nm and less, while a height of the material 132 may be 50-100 nm and more, depending on the overall device and process requirements. Since the electric performance of the gate electrode structures 130 may no longer be appropriate for many types of performance driven field effect transistors, it has been proposed to replace the well-established materials silicon dioxide and polysilicon by more sophisticated material systems, such as high-k dielectric materials in combination with highly conductive electrode metals. Since the implementation of any such sophisticated material systems in an early manufacturing stage, i.e., upon forming the gate electrode structures 130, is very complex, in other approaches, the gate electrode structures 130 are formed on the basis of well-established materials and patterning strategies and at least the polysilicon material 132 is to be placed in a later manufacturing stage, i.e., after performing any high temperature treatments and other critical processes, which may otherwise result in a shift or variation of the electronic characteristics of sophisticated gate electrode structures. To this end, in some well-established strategies, an interlayer dielectric material 120 is typically provided above the gate electrode structures 130. For this purpose, well-established materials, such as silicon nitride and silicon dioxide, are frequently used, for instance in the form of a silicon nitride layer 121 that may act as an etch stop material during the further processing of the device 100 and which may also provide superior diffusion stopping capabilities, for instance in terms of avoiding copper diffusion into sensitive device areas upon forming a complex metallization system on the basis of copper and low-k dielectric materials. Furthermore, a silicon dioxide layer 122 is typically provided above the silicon nitride material 121 and provides the desired chemical and mechanical characteristics for passivating any circuit elements formed in and above the semiconductor layer 102. Consequently, depending on the density of gate electrode structures 130 and the geometry thereof, a more or less pronounced surface topography is created upon forming the interlayer dielectric material 120, thereby also requiring a certain degree of overfilling in order to reliably fill the spaces between the individual circuit elements 130.
The device 100 as illustrated in FIG. 1a may be formed on the basis of well-established process techniques including sophisticated lithography and etch techniques for patterning the gate electrode structures 130, followed by any further processes for forming drain and source regions of any appropriate profile in the semiconductor layer 102 associated with appropriate high temperature anneal processes. Thereafter, the materials 121 and 122 are deposited on the basis of well-established process techniques, such as plasma enhanced chemical vapor deposition (CVD) and the like. As discussed above, for a replacement gate approach, the polysilicon material 132 is to be exposed in order to enable an efficient removal of this material and the deposition of sophisticated gate materials, such as high-k materials, work function metals, highly conductive electrode metals and the like. In order to remove any excess portion of the interlayer dielectric material 120, typically a CMP process 110 or a sequence of CMP processes is applied. In a first step or phase of the process 110, the excess portion of the silicon dioxide material 122 is removed, which may be accomplished on the basis of well-established process recipes, for instance by using available standard slurry materials including silica particles as abrasive particles. On the basis of any such available slurry solutions, appropriate process conditions can be established in order to remove the material 122 at removal rates enabling a desired high controllability. Consequently, an efficient smoothing of the surface topography may be accomplished during the advance of the polishing process when removing a portion of the material layer 122.
FIG. 1b schematically illustrates the device 100 in an advanced stage of the process 110, in which increasingly the material of the silicon nitride layer 121 on top of the gate electrode structures 130 is exposed. Available slurry materials including silica, however, typically exhibit a much higher removal rate for silicon dioxide material and also for polysilicon material relative to the removal rate for silicon nitride material, which may be taken advantage of by using the silicon nitride material 121 as a stop layer. On the other hand, upon continuing the removal process on the basis of these slurry materials, the reduced removal rate of the silicon nitride material may require pronounced process times to remove the exposed portion of the layer 121 and to finally remove the dielectric cap material 133, which would result in undue recessing of the silicon dioxide material 122. It would, therefore, be desirable to continue the further removal process on the basis of substantially non-selective process conditions, which, however, may require a sophisticated slurry material that provides similar etch rates of silicon dioxide and silicon nitride, while at the same time, at a final phase of the removal process, polysilicon material also has to be removed to a certain degree in order to ensure a reliable exposure of the polysilicon material, since any nitride residues would unduly affect the further processing of the device.
It turns out, however, that the limited number of commercially available slurry solutions having a substantially matched removal rate for silicon dioxide and silicon nitride have to be used within a very narrow process window, thereby contributing to a reduced degree of controllability, since any small variations in process conditions may result in an over-proportional deviation of the process result. Furthermore, the commercially available slurry solutions may show a pronounced dependence on the pattern density, that is, the removal rates may generally be different above densely packed device areas relative to less dense device regions.
FIG. 1c schematically illustrates a typical process result obtained on the basis of commercially available slurry solutions, wherein a certain degree of recessing may be observed in the polysilicon material 132 and, in particular, in the silicon dioxide material 122, which may negatively affect the further processing. For example, the recessing in the polysilicon material 132 may result in minute silicon nitride residues located at the edge of the gate electrode structures 130, which may cause an incomplete removal of the material 132 during the subsequent complex etch process. On the other hand, the recessing of the silicon dioxide material 122 may provide very sophisticated process conditions upon refilling the gate electrode structures 130 by metal materials and removing any excess metal from the gate electrode structures 130. In this case, the recessed areas in the silicon dioxide material may require excessive overpolish times in order to reliably remove any metal residues, thereby generally reducing the overall height of the gate electrode structures, while nevertheless a certain probability of leaving any metal residues and, thus, leakage paths may exist.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.